• DocumentCode
    3119525
  • Title

    Evaluating high leakage effects of low VTH circuits using high VTH devices

  • Author

    Miyazaki, Toshimasa ; Sakurai, Takayasu

  • Author_Institution
    Inst. of Ind. Sci., Univ. of Tokyo, Japan
  • fYear
    2004
  • fDate
    22-25 March 2004
  • Firstpage
    241
  • Lastpage
    244
  • Abstract
    A scheme to emulate leakage current of low threshold voltage MOSFETs using high threshold voltage MOSFETs is proposed. The leakage current at any threshold voltage lower than the original threshold voltage can be emulated without any changes in the manufacturing process. Furthermore, a single test structure can be used to measure the subthreshold leakage current at various threshold voltages. The DIBL (Drain Induced Barrier Lowering), source control, and substrate bias effects can be reproduced by the scheme. A test chip is manufactured and measured to show the validity of the proposed leakage emulator.
  • Keywords
    MOSFET; SPICE; VLSI; leakage currents; low-power electronics; semiconductor device models; CMOS process; NMOS transistor; SPICE model; VLSI chip; drain induced barrier lowering; high leakage effects; high threshold voltage MOSFET; inverter ring oscillator; leakage current emulation; low threshold voltage MOSFET; single test structure; substrate bias effects; subthreshold leakage current; Circuit testing; Current measurement; Leakage current; MOSFET circuits; Manufacturing processes; SPICE; Semiconductor device measurement; Very large scale integration; Virtual manufacturing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on
  • Print_ISBN
    0-7803-8262-5
  • Type

    conf

  • DOI
    10.1109/ICMTS.2004.1309487
  • Filename
    1309487