Effects of intra chip topography in back end of line processes on focus leveling control and process window degradation with high NA exposures

Modern High NA exposure systems trade off process depth of focus for gains in image resolution. The ever increasing Lens NA and associated loss of process window put greater demands on focus and leveling control as well as product design in order to gain back process capability. Poor chip design combined with multi level Back End of Line structures can create local topographies that exceed the focus budget of a modern High NA lens. The impact of these complications can be a significantly narrowed process window and increased ACLV. Advanced multi-point focusing and die-by-die leveling methods attempt to gain back focus window lost due to increased lens NA and wafer topography. In this paper we correlate surface topography and chip design to focus and leveling problems. Step height differences between Kerf and product surfaces were measured using AFM. Leveling tilts and effect on DOF were evaluated using FEM methods. ASML leveling metrology methods such as Dynamic Leveling, Local Offset Profile, Static Local Leveling, Static Global Leveling, and the use of Fixed Leveling Offsets were evaluated with respect to improving process windows and ACLV.