Title :
SPEED-a highly flexible slice structure and datapath generator
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
A novel generator for bit-slice and datapath structures is presented. It is a multipurpose macrocell generator usable in high-speed applications. The main features are a high degree of architectural, functional, and topological flexibility as well as electrical and geometrical optimization capabilities. The datapath is based on a bus-oriented architecture. The number of internal buses is arbitrary. Since the generation of a control unit for basic decoding and internal clock distribution is optional, there is no overhead if a circuit consists of several datapaths. Testability and design-rule updatability concepts are covered
Keywords :
bit-slice computers; circuit layout CAD; microprocessor chips; SPEED; bit slice structure generator; bus-oriented architecture; clock distribution; datapath generator; design-rule updatability concepts; electrical optimisation capability; features; flexibility; geometrical optimization capabilities; high-speed applications; internal buses; multipurpose macrocell generator; testability concepts; Application software; Circuit testing; Clocks; Data engineering; Decoding; Design engineering; Latches; Pipeline processing; System buses; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20868
