A 20 NS CMOS programmable logic device for asynchronous applications

Author

Pathak, Jagdish ; Douglass, Steve ; Vider, Dov-Ami ; Mulder, Theodor ; Arreola, Jose ; Mehta, Sunil

Author_Institution

Cypress Semicond. Corp., San Jose, CA, USA

fYear

1988

fDate

16-19 May 1988

Abstract

A 20-ns, 600-mW, programmable logic device (PLD) using 0.8-μm, two-layer metal, n-well CMOS EPROM technology is described. This PLD´s architecture is optimized for asynchronous applications. It is a 28-pin device with 13 inputs, 12 I/Os, one V_CC and two V_SS pins. Each I/O pin has a macrocell which includes an input and an output register, and control muxes for output enable and feedback to the array. Product terms generate set, reset, and clock for each register independently. A product term input to the XOR gate can configure the D register into a JK, RS or T flip-flop. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses substrate bias generator to improve performance and latchup immunity

Keywords

CMOS integrated circuits; PROM; cellular arrays; integrated logic circuits; 20 ns; 28-pin device; 600 mW; 800 nm; CMOS programmable logic device; D register; JK flip flop; PLD; RS flip flop; T flip-flop; XOR gate; asynchronous applications; compensated for process variations; control muxes; feedback; latchup immunity; macrocell; n-well CMOS EPROM technology; optimized for speed; output enable; sense amplifier; substrate bias generator; two-layer metal; CMOS technology; Clocks; EPROM; Flip-flops; Macrocell networks; Output feedback; Pins; Power amplifiers; Programmable logic devices; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/CICC.1988.20870

Filename

20870