DocumentCode
3121059
Title
Wafer-level 3D manufacturing issues for streaming video processors
Author
Zeng, A.Y. ; Lu, J.-Q. ; Gutman, R.J. ; Rose, K.
Author_Institution
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
fYear
2004
fDate
4-6 May 2004
Firstpage
247
Lastpage
251
Abstract
The performance of both 2D and 3D implementations of a streaming video processor is presented incorporating 130 nm technology node parameters. The reduced memory access time predicted for the 4 MB L2 cache (0.9 ns for 3D and 1.65 ns for 2D) is indicative of performance advantages projected for 3D implementations of memory-intensive architectures.
Keywords
cache storage; digital signal processing chips; high definition television; integrated circuit interconnections; integrated circuit manufacture; manufacturing processes; memory architecture; television receivers; video coding; video signal processing; wafer bonding; 0.9 ns; 1.65 ns; 130 nm; 4 MB; cache storage; high definition television; integrated circuit interconnections; memory access time; memory intensive architectures; streaming video processors; wafer level 3D manufacturing; Copper; Dielectrics; HDTV; High definition video; Manufacturing processes; Streaming media; System-on-a-chip; TV; Wafer bonding; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop
Print_ISBN
0-7803-8312-5
Type
conf
DOI
10.1109/ASMC.2004.1309576
Filename
1309576
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