Title :
A 2500 gate programmable logic device with subdivisable macrocells
Author :
Gudger, Keith H. ; Gongwer, Geoffrey S.
Author_Institution :
ATMEL Corp., San Jose, CA, USA
Abstract :
A 2500-gate programmable logic device with a 25-ns typical propagation delay is described. This CMOS EPROM device has less than 50-mW power dissipation. Its simple, regular architecture is supported by industry-standard third-party software tools. Global routing and subdivisable macrocells provide gate utilization factors equivalent to gate arrays
Keywords :
CMOS integrated circuits; PROM; VLSI; cellular arrays; integrated logic circuits; 25 ns; 2500-gate programmable logic device; 50 mW; CMOS EPROM device; gate utilization factors; industry-standard third-party software tools; power dissipation; propagation delay; regular architecture; subdivisable macrocells; Circuit testing; EPROM; Flip-flops; Integrated circuit interconnections; Logic arrays; Logic devices; Macrocell networks; Pins; Programmable logic arrays; Programmable logic devices;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20871
