Hardware-based parallel firefly algorithm for embedded applications

The firefly algorithm (FA) is a new population-based metaheuristic bioinspired on the behavior of the flashing characteristics of fireflies. As a population-based algorithm, the FA suffers from large execution times specifically for embedded optimization problems with computational limitations. For reducing execution times we propose a hardware parallel architecture of the FA algorithm that facilitates the implementation in Field Programmable Gate Arrays (FPGAs). In addition, this work proposes the application of the opposition-based learning (OBL) approach to the FA algorithm. The respective hardware implementation (HPOFA) was mapped into a Virtex5 FPGA device and numerical experiments using four well-known benchmark problems demonstrate that the opposition-based approach allows the FA algorithm to improve its functionality, preserving the swarm diversity and avoiding the premature convergence problem. Synthesis results point out that the HPOFA architecture is effectively mapped in hardware and is suitable for embedded applications.