Hardware realization of GALS based cortical column systems

Many researchers seek for alternatives to traditional computing architectures, often placing emphasis on modeling biological systems that possess intelligence and learning capabilities. Cortical columns have emerged as a high-level unsupervised learning model for extracting independent data features in a hierarchical manner. Previous cortical models simply rely on software based techniques and neglect the actual purpose of investigating these architectures: to diverge from the conventional Von Neumann approach to an actual hardware realization of an intelligent system. This work presents the hardware realization of a Globally Asynchronous Locally Synchronous (GALS) cortical column system, taking hardware based factors into consideration which were previously disregarded by software models. We introduce a Neural Spike Dual-Rail encoding scheme for GALS communication, and a temporal pooling unit capable of detecting data distortions during training and testing. This work concludes with a study on cortical columns and their hierarchical impact on hardware resources.