DocumentCode
3121611
Title
Bus I/O register intensive user-configurable microprocessor peripheral
Author
Hung, Chuan-Yung ; Chan, Yiu-Fai
Author_Institution
Altera Corp., Santa Clara, CA, USA
fYear
1988
fDate
16-19 May 1988
Abstract
A CMOS erasable programmable logic device (EPLD) optimized for microprocessor peripheral and bus control applications is described. In addition to a general-purpose EPLD core and 52 user-configurable registers, the dedicated peripheral I/O logic can be programmed by the control macrocells to interface directly to all known microprocessor families. An I/O bus port with 24-mA drive capability allows direct connection to a microprocessor bus
Keywords
CMOS integrated circuits; cellular arrays; integrated logic circuits; 24 mA; 24-mA drive capability; CMOS; EPLD; I/O bus port; I/O register intensive; bus control applications; bus interface; direct interfacing; erasable programmable logic device; general-purpose EPLD core; macrocells; peripheral interface; user-configurable microprocessor peripheral; user-configurable registers; Clocks; Computer architecture; Feedback; Flip-flops; Latches; Logic arrays; Macrocell networks; Microprocessors; Registers; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20874
Filename
20874
Link To Document