Attack and resolution of a major product-specific systematic yield loss problem

This paper presents a case study in the identification and resolution of a product-specific systematic yield loss problem. The approach taken employed multiple parallel avenues of investigation including critical area analysis, analysis of wafer and chip level data from Automatic Test Equipment (ATE), failure mode analysis, and, most notably, the use of yield diagnostic software applications. The unique signature of this problem was linked to an inter-level dielectric deposition process. A short loop method was devised to quickly evaluate a number of potential solutions. The most promising solutions were evaluated using product wafers. Robustness to the failure mechanism and impact on throughput were the two main considerations in selecting the final solution. This work resulted in a dramatic improvement in yield for this product.