Title :
Gate array design productivity: an empirical investigation
Author :
Fey, C.F. ; Paraskevopoulos, D.E.
Author_Institution :
Xerox, Corp., Webster, NY, USA
Abstract :
An empirical model of design productivity is presented. The model is derived from 55 designs of four major corporations. It fits the data with a median error of 14%. The model estimates design productivity, which enables determinations of manpower and schedules. It also normalizes productivity for differences in the design tasks, enabling standardized productivity measurement for planning and for benchmarking
Keywords :
PLD programming; cellular arrays; benchmarking; design productivity; empirical investigation; empirical model; gate array design; major corporations; manpower; planning; schedules; standardized productivity measurement; Circuit testing; Costs; Fabrication; Job shop scheduling; Manufacturing processes; Measurement standards; Microelectronics; National electric code; Productivity; Semiconductor device modeling;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20876
