Development cost and size estimation starting from high-level specifications

Author

Fornaciari, William ; Salice, Fabio ; Bondl, U. ; Magini, Edi

Author_Institution

Politecnico di Milano, Italy

fYear

2001

fDate

2001

Firstpage

86

Lastpage

91

Abstract

This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark, the LEON-1 microprocessor, whose VHDL description is of public domain

Keywords

formal specification; hardware description languages; hardware-software codesign; performance evaluation; COCOMO analysis; LEON-1 microprocessor; VHDL function point metric; VHDL-based designs; benchmark; cost estimation; development cost; high-level specifications; partial high-level description; project size prediction methodology; size estimation; Business; Concurrent engineering; Costs; Design methodology; Engineering management; Microprocessors; Permission; Predictive models; Project management; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Codesign, 2001. CODES 2001. Proceedings of the Ninth International Symposium on

Conference_Location

Copenhagen

Print_ISBN

1-58113-364-2

Type

conf

DOI

10.1109/HSC.2001.924656

Filename

924656