Evaluating register file size in ASIP design

Author

Jain, Manoj Kumar ; Wehmeyer, Lars ; Steinke, Stefan ; Marwedel, Peter ; Balakrishnan, M.

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Delhi, India

fYear

2001

fDate

2001

Firstpage

109

Lastpage

114

Abstract

Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this paper we observe the effect of changing register file size on the performance as well as power and energy consumption. Detailed data is generated and analyzed for a number of application programs. Results indicate that choice of an appropriate number of registers has a significant impact on performance

Keywords

application specific integrated circuits; instruction sets; parallel processing; ASIP design; application programs; application requirements; application specific instruction set processors; architectural features; constraints; performance; register file size; Aerospace electronics; Application specific processors; Automatic control; Computer science; Control system synthesis; Costs; Data flow computing; Permission; Registers; Space exploration;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Codesign, 2001. CODES 2001. Proceedings of the Ninth International Symposium on

Conference_Location

Copenhagen

Print_ISBN

1-58113-364-2

Type

conf

DOI

10.1109/HSC.2001.924660

Filename

924660