Analysis of computational energy efficiency in single-flux-quantum electronics by implementing an integer-based hardware-algorithm

Author

Xu, Qi ; Shimamura, Y. ; Yamanashi, Y. ; Yoshikawa, N. ; Ortlepp, Thomas

Author_Institution

Dept. of Electr. & Comput. Sci., Yokohama Nat. Univ., Yokohama, Japan

fYear

2013

fDate

7-11 July 2013

Firstpage

1

Lastpage

3

Abstract

We designed and implemented a single-flux-quantum (SFQ) based hardware-algorithm known as the 3n+1 conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator and a central processor. This design can perform with a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW based on the AIST 10 kA/cm² advanced Nb process. The power consumption was further reduced by using an LR-biasing approach.

Keywords

superconducting logic circuits; 3n+1 conjecture; LR-biasing approach; SFQ based hardware-algorithm; central processor; computational energy efficiency; frequency 90 GHz; high-frequency clock generator; integer register; integer-based hardware-algorithm; power consumption; single-flux-quantum electronics; word length 16 bit; Adders; Clocks; Generators; Niobium; Power demand; Radiation detectors; Shift registers; LR-biasing approach; SFQ circuit; bit energy;

fLanguage

English

Publisher

ieee

Conference_Titel

Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International

Conference_Location

Cambridge, MA

Print_ISBN

978-1-4673-6369-3

Type

conf

DOI

10.1109/ISEC.2013.6604280

Filename

6604280