Integrated pin electronics for VLSI functional testers

A novel method is presented for building high-performance pin electronics circuitry using conventional CMOS technology. To demonstrate the feasibility of these circuit techniques, a prototype processing-element chip consisting of four I/O channels was designed in a 2-μm double-metal CMOS technology. It contains 13 K transistors in a die size of 3.9 mm×5.3 mm. Running at 33 Mvectors/s, the chip dissipates 125 mW with a 5-V supply. The authors feel that it is possible to build practical integrated pin electronics for functional VLSI testers with a technology only as good as that of the design under test