Title :
A methodology for the test of embedded compiled cells
Author :
Samad, M. Arif ; Butzerin, Teresa
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
The use of compilers for structured cells such as RAMs, ROMs, multipliers and PLAs (programmable logic arrays) has become widespread in the design of application-specific integrated circuits (ASICs). The authors present a methodology for testing circuits made from these compiled cells. The key elements of this methodology are the vector compilers that generate test suites for the compiled cells and an isolation strategy that allows these test suites to be applied to embedded functional blocks
Keywords :
cellular arrays; integrated circuit testing; integrated logic circuits; integrated memory circuits; logic testing; ASICs; PLAs; RAMs; ROMs; application-specific integrated circuits; embedded compiled cells; embedded functional blocks; isolation strategy; monolithic IC; multipliers; programmable logic arrays; test suite generation; testing; vector compilers; Application specific integrated circuits; Circuit faults; Circuit testing; Integrated circuit technology; Program processors; Programmable logic arrays; Read only memory; Shape; Timing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20883
