DocumentCode :
3123154
Title :
A 45ns 64Mb DRAM With A Merged Match-line Test Architecture
Author :
Mori, Shigeru ; Miyamoto, Hiroshi ; Morooka, Yoshikazu ; Kikuda, Shigeru ; Suwa, Makoto ; Kinoshita, Mitsuya ; Hachisuka, Atsushi ; Arima, Hideaki ; Yamada, Michihiro ; Yoshihara, Tsutomu ; Kayano, Shinpei
Author_Institution :
Mitsubishi Electric Corporation
fYear :
1991
fDate :
13-15 Feb. 1991
Firstpage :
110
Lastpage :
298
Keywords :
Circuit testing; Decoding; Laboratories; Large scale integration; Lithography; Mirrors; Random access memory; Read-write memory; Redundancy; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-87942-644-6
Type :
conf
DOI :
10.1109/ISSCC.1991.689085
Filename :
689085
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3123154
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