A 33ns 64Mb DRAM

Author

Oowaki, Y. ; Tsuchida, K. ; Watanabe, Y. ; Takashima, D. ; Ohta, M. ; Nakano, H. ; Watanabe, S. ; Nitayama, A. ; Horiguchi, F. ; Ohuchi, K. ; Masuoka, F. ; Hara, H.

Author_Institution

Toshiba Corporation

fYear

1991

fDate

13-15 Feb. 1991

Firstpage

114

Lastpage

299

Keywords

CMOS process; Circuit testing; Differential amplifiers; Random access memory; Solid state circuits; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-87942-644-6

Type

DOI

10.1109/ISSCC.1991.689087

Filename

689087

Link To Document