Coherent BPSK demodulator using Costas loop and early-late gate synchronizer

Author

Shachi, P. ; Mishra, Ravishankar ; Jatoth, Ravi Kumar

Author_Institution

Dept. of ECE, NIT Warangal, Warangal, India

fYear

2013

fDate

4-6 July 2013

Firstpage

1

Lastpage

6

Abstract

The paper presents the design of a digital transceiver with binary phase-shift-keying (BPSK) modulation scheme. The resulting transmitter communicates 4 Kbps data modulating a 128KHz carrier, with receiver sampling frequency of 2MHz. The receiver compensates for frequency and phase errors caused by various sources like clock drifts, Doppler shift and bit-time errors. The Costas loop and Early-Late Gate (ELG) Synchronizer are used for coherent data detection. The simulation has been carried out using MATLAB Simulink and Modelsim PE and each module is verified for its working. Finally the design is implemented on Xilinx Spartan 3 FPGA to verify its behavior in real-time environment.

Keywords

Doppler shift; demodulation; demodulators; field programmable gate arrays; phase shift keying; synchronisation; transceivers; Costas loop; Doppler shift; ELG synchronizer; Modelsim PE; Xilinx Spartan 3 FPGA; binary phase-shift-keying modulation scheme; bit-time error; clock drift; coherent BPSK demodulator; coherent data detection; data modulation; digital transceiver; early-late gate synchronizer; receiver sampling frequency; BPSK; Costas loop; Early-late gate synchronizer and phase and frequency offsets; NCO (Numerically Controlled Oscillator);

fLanguage

English

Publisher

ieee

Conference_Titel

Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on

Conference_Location

Tiruchengode

Print_ISBN

978-1-4799-3925-1

Type

conf

DOI

10.1109/ICCCNT.2013.6726622

Filename

6726622