Statistical design for variation tolerance: key to continued Moore´s law

Author

Karnik, Tanay ; De, Vivek ; Borkar, Shekhar

Author_Institution

Circuit Res., Intel Labs, Hillsboro, OR, USA

fYear

2004

fDate

2004

Firstpage

175

Lastpage

176

Abstract

Future high performance microprocessor design with technology scaling beyond 90nm will face a major challenge - parameter variations. Design practice will have to change from deterministic design to statistical design for variation tolerance. This paper discusses process, voltage and temperature variations, and their impact on circuits and microarchitecture. Possible solutions to reduce the impact of parameter variations on digital and analog circuits, and to achieve higher target frequencies are also presented.

Keywords

CMOS digital integrated circuits; circuit CAD; integrated circuit design; microprocessor chips; nanoelectronics; statistical analysis; tolerance analysis; CMOS technology; body bias; continued Moore´s law; high performance design; microarchitecture; microprocessor design; parameter variation; pipelining; process variations; statistical design; switching activity; technology scaling; temperature variations; variable offset cancellation technique; variation tolerance; voltage variations; CMOS logic circuits; CMOS technology; Degradation; Frequency; Microarchitecture; Microprocessors; Moore´s Law; Packaging; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309939

Filename

1309939