Analog front-end and power management integration on a 0.13 μm CMOS ADSL SoC

Author

Oswal, S. ; Mujica, F. ; Prasad, S. ; Srinivasa, R. ; Sharma, Bhanu P ; Raychoudhary, A. ; Khasnis, H. ; Sharma, Ashok ; Sriram, R. ; Vijayvardhan, B. ; Menon, R. ; Gireesh, R. ; Ahuja, N. ; Gambhir, M. ; Sadafale, M.

Author_Institution

Broadband Silicon Technol. Center, Texas Instrum., Inc., USA

fYear

2004

fDate

2004

Firstpage

193

Lastpage

198

Abstract

This paper describes the analog and power management aspects of a single chip asymmetric digital subscriber line (ADSL) customer premises equipment (CPE) router. We address the system partitioning between analog and digital resulting in optimum system cost and performance for a .13 μm CMOS process.

Keywords

CMOS integrated circuits; digital subscriber lines; mixed analogue-digital integrated circuits; system-on-chip; telecommunication network routing; transceivers; CMOS ADSL SoC; CMOS process; analog front-end integration; customer premises equipment router; discrete multi-tone modulation; high-level system requirements; high-linearity driver; optimum system cost; optimum system performance; power management integration; single chip asymmetric digital subscriber line; switchable downstream data rate; system partitioning; CMOS process; CMOS technology; Costs; DSL; Energy management; Frequency; Low pass filters; OFDM modulation; Power system management; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309944

Filename

1309944