A very-high-frequency CMOS four-quadrant analogue multiplier

A new CMOS four-quadrant analogue multiplier which consists of three high speed unity-gain buffers and two NMOS transistors operated in the triode region is presented. Simulation results based on TSMC 0.6 μm SPDM process parameters indicate for supply voltages of ±2.5 V, the linearity error can be kept below 5% for a differential input voltage range up to ±1 V. Total harmonic distortion at 10 MHz with a 1 V (peak) input signal at either input terminal with a ±1 V DC voltage at the other terminal is less than 5%. The simulated -3 dB bandwidth of this multiplier is about 230 MHz