DocumentCode
3124969
Title
A 13000 gate 3 layer metal bipolar gate array
Author
Coy, Bruce ; Mai, An ; Yuen, Ray
Author_Institution
Appl. MicroCircuits Corp., San Diego, CA, USA
fYear
1988
fDate
16-19 May 1988
Abstract
A 13000 gate ECL TTL (emitter-coupled logic/transistor-transistor logic) bipolar logic array featuring 100-ps/gate delay has been developed. A revolutionary design technique was used to significantly reduce the worst-case power consumptions to less than 10 W. A bipolar channelless architecture helps minimize interconnect delay, but still maintains cell utilization to well over 95% without the use of quad-level metal
Keywords
bipolar integrated circuits; cellular arrays; emitter-coupled logic; integrated logic circuits; large scale integration; transistor-transistor logic; 10 W; 100 ps; ECL; TTL; bipolar channelless architecture; bipolar gate array; emitter-coupled logic; power consumptions; three layer metallisation; transistor-transistor logic; Capacitors; Coupling circuits; Delay; Geometry; Integrated circuit interconnections; Logic arrays; Resistors; Routing; Temperature; Thermal management;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20896
Filename
20896
Link To Document