Time delay measurement methods for integrated transmission lines and high speed cell characterization

In high speed integrated circuits, the time delays on interconnects become critical. An approximate solution based on capacitive and RC models for simulation is often not appropriate to describe critical paths where delays under 100 ps are to be considered. In such cases, long interconnections should be considered as transmission lines placed over a highly dispersive material. We developed new models for accurate simulation of interconnect lines on semiconductor substrate, and this paper deals with an experimental method to validate such models under real conditions. This paper presents new methods to measure the delays between two interconnected points, where the finite size of the buffer and transmission line parameters are considered. The proposed method was implemented in a CMOS demonstrator integrated circuit based on a sea-of-gate structure. This allows one to study various interconnection configurations which aim at improving the propagation of high speed signals The method can also be extended to on chip dynamic characterization of various complex cells operating at high speed