DocumentCode
3125141
Title
SH 100E 10000 gate ECL/15000 gate CML gate array family with ECL/TTL I/O compatibility
Author
Franz, M. ; Delker, K. ; Whang, T.C. ; Wilhelm, W.
Author_Institution
Siemens Components Inc., Santa Clara, CA, USA
fYear
1988
fDate
16-19 May 1988
Abstract
A novel bipolar gate array family is described. The family consists of four arrays and two macro libraries. With ECL (emitter-coupled logic), complexity ranges from 1500 to 10 000 equivalent gates, and with CML (current-mode logic), complexity covers 2250 to 15000 equivalent gates. Both CML and ECL macros can be mixed on any customer-defined chip. This novel duality allows tradeoffs between performance, power, and complexity on the same chip. The I/Os are designed to serve both ECL and TTL interfaces
Keywords
bipolar integrated circuits; cellular arrays; emitter-coupled logic; integrated logic circuits; large scale integration; CML; ECL/TTL I/O compatibility; SH 100E; bipolar gate array family; current-mode logic; emitter-coupled logic; macro libraries; Capacitance; Circuit synthesis; Delay; Energy management; Frequency; Isolation technology; Logic arrays; Resistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20897
Filename
20897
Link To Document