A 72 K CMOS channellers gate array with embedded 1 Mbit dynamic RAM

Author

Sawada, Kazuhiro ; Sakurai, Takayasu ; Nogami, Kazutaka ; Iizuka, Tetsuya ; Uchino, Y. ; Tanaka, Yuichi ; Kobayashi, Takehiko ; Kawagai, K. ; Uchino, Y. ; Tanaka, Yuichi ; Kobayashi, Takehiko ; Kawagai, K. ; Ban, Eiji ; Shiotari, Yoshihisa ; Itabashi, Yas

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1988

fDate

16-19 May 1988

Abstract

A 1-Mb DRAM (dynamic random-access memory) is embedded in a 72-K-raw-gates channelless gate array fabricated in 1.0-μm HC²MOS twin-well technology. The DRAM design is optimized for embedding, such as the adaptation of no substrated bias design and p-well protected n-channel memory cells. The typical delay time of the gate array is 0.4 ns, and the worst-case access time of the DRAM is 60 ns

Keywords

CMOS integrated circuits; VLSI; cellular arrays; integrated logic circuits; random-access storage; 0.4 ns; 1 Mbit; 1 micron; 60 ns; 72 K array; CMOS channellers gate array; HC²MOS twin-well technology; VLSI; access time; delay time; dynamic RAM; dynamic random-access memory; embedded DRAM; p-well protected n-channel memory cells; Artificial intelligence; Body sensor networks; DRAM chips; Delay; Fluctuations; Protection; Random access memory; Read-write memory; Semiconductor devices; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/CICC.1988.20898

Filename

20898