Title :
A sub half-ns 237 K gate CMOS compacted array
Author :
Hui, Alex ; Wong, Anthony ; Szeto, Roger ; Yeh, Stanley ; Kao, Chi-yi ; Wong, Daniel ; Tse, Yvone
Author_Institution :
LSI Logic Corp., Santa Clara, CA, USA
Abstract :
A family of third-generation compacted arrays with up to 237 K gates has been developed using a channelless architecture. 1-μm HCMOS (high-speed complementary metal-oxide semiconductor) technology with 0.75-μm effective channel length was used to fabricate the device. Complex designs with up to 100 K utilized gates can be implemented on a single chip using this technology. Switching performance of 400 ps is achieved on two input NAND gates with typical loading
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; integrated logic circuits; 0.75 micron; 1 micron; 237 K gates; 400 ps; CMOS compacted array; HCMOS; VLSI; channelless architecture; effective channel length; logic IC; third-generation; Circuit testing; Costs; Delay; Integrated circuit interconnections; Libraries; Logic arrays; Logic devices; MOSFETs; Macrocell networks; Routing;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20899
