Title :
A new dual-mode data compressing A/D converter
Author :
Lampinen, Harri ; Vainio, Olli
Author_Institution :
Signal Process. Lab., Tampere Univ. of Technol., Finland
Abstract :
A new data compressing analog-to-digital converter has been designed and implemented. The converter combines a successive-approximation converter architecture with a novel control algorithm, allowing operation in both linear and data compressing modes. An experimental chip has been constructed in a 1.2 μm double-metal double-poly CMOS process, and demonstrates over 4.5 Mhz sampling rate
Keywords :
CMOS integrated circuits; analogue-digital conversion; data compression; integrated circuit design; 1.2 micron; 4.5 MHz; data compressing mode; double-metal double-poly CMOS process; dual-mode data compressing A/D converter; linear compressing mode; sampling rate; successive-approximation converter architecture; CMOS process; Capacitors; Laboratories; Sampling methods; Semiconductor device measurement; Signal processing; Signal processing algorithms; Speech coding; Switches; Time measurement;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.608759
