Title :
A 120 K-gate usable CMOS sea of gates packing 1.3 M transistors
Author :
Suehiro, Yoshiyuki ; Miura, Daisuke ; Naitoh, Mitsugu ; Tsutsumi, Sadao ; Shirato, Takehide
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
A CMOS sea of gates with 160 K basic cells for random logic and memories is reported. Because of the unique architecture, the LSI offers flexible configuration of RAMs, ROMs, and PLAs (programmable logic arrays) with high density and suitable routing areas for random logic circuits, and results in the utilization of 120 K basic cells. It is fabricated with CMOS 1.0-μm triple-metal-layer process technology
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; integrated logic circuits; integrated memory circuits; random-access storage; read-only storage; 1 micron; 120 K gate configuration; CMOS; LSI; PLAs; RAMs; ROMs; memories; programmable logic arrays; random logic circuits; sea of gates; triple-metal-layer process technology; CMOS logic circuits; CMOS process; CMOS technology; Large scale integration; Logic circuits; Programmable logic arrays; Random access memory; Read only memory; Routing; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20900
