A systolic architecture for discrete wavelet transforms

We present an integrated systolic architecture for computation of the one-dimensional discrete wavelet transform (DWT) of signals. This integrated architecture is useful for both decomposition (forward DWT) and reconstruction (inverse DWT) of signals. The architecture has been designed based on an efficient systolic algorithm suitable for high speed VLSI implementation. This integrated systolic architecture is very unique in the sense that the same architecture is used for forward DWT and inverse DWT by selecting some suitable control signals and this systolic architecture yields 100% utilization unlike many other existing architectures in the literature. The two-dimensional DWT architecture can easily be designed by extending this one-dimensional solution