DocumentCode :
3126635
Title :
Programmable Graph Architectures (PGAs) for Matrix Multiplications and Transposes
Author :
Tang, K. Wendy ; Oruc, A. Yavuz
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York at Stony Brook, Stony Brook, NY, USA
fYear :
2009
fDate :
28-29 Dec. 2009
Firstpage :
373
Lastpage :
378
Abstract :
Configurable computing (CC) that combines the computational benefits of custom ASICs and flexibility and reconfigurability of general-purpose microprocessor has opened a new and exciting era for designing mobile software services. In particular, the increased computational density of programmable logic devices has the potential to lead to real-time mobile software and services that require fast matrix computations without having to perform row/column inner product operations at all. In this paper, we introduce a direct mapping between matrix groups and Cayley graphs to propose a novel architecture for matrix operations on configurable devices that can facilitate real-time mobile software and services requiring fast matrix operations such as various video manipulations. This new family of architectures is based on Cayley graphs, hence the name programmable graph architecture (PGA). The basic idea of the PGA is to transform the original matrix operation into a spatial graph routing problem. Our previous work of using Cayley Graphs as an interconnection network model has provided the backbone of this new approach for carrying out matrix operations on programmable graph architectures. A step-by-step algorithm and an example will be used to illustrate our approach.
Keywords :
graph colouring; matrix algebra; mobile computing; programmable logic devices; Cayley graphs; configurable computing; interconnection network model; matrix multiplications; matrix transposes; programmable graph architectures; programmable logic devices; real-time mobile software services; spatial graph routing problem; Computer architecture; Electronics packaging; Microprocessors; Mobile computing; Multiprocessor interconnection networks; Programmable logic devices; Routing; Software design; Software performance; Spine; configurable computing; matrix operations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wireless Networks and Information Systems, 2009. WNIS '09. International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-0-7695-3901-0
Electronic_ISBN :
978-1-4244-5400-6
Type :
conf
DOI :
10.1109/WNIS.2009.95
Filename :
5381981
Link To Document :
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