Area- and power-efficient 2D analog filters employing multirate signal processing techniques

A major difficulty in the realization of two-dimensional (2D) analog filters concerns the large size of the delay-line (DL) memory blocks that are needed for line storage and which, in turn, lead to very large chip area and power dissipation due to the capacitive nature of the analog storage cells. This paper demonstrates the practical realization of an analog CMOS prototype chip for real-time image processing where multirate techniques are efficiently employed to downsize the DL memory blocks. Compared to currently available solutions this yields a more economic solution both for silicon area and power dissipation