DocumentCode

3126898

Title

A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit

Author

Lai, B. ; Walker, R.C.

Author_Institution

Hewlett-Packard

fYear

1991

fDate

13-15 Feb. 1991

Firstpage

144

Lastpage

306

Keywords

Circuits; Clocks; Data mining; Electrons; Phase detection; Phase frequency detector; Production; Prototypes; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-87942-644-6

Type

conf

DOI

10.1109/ISSCC.1991.689102

Filename

689102