Title :
FPGA Implementations of BCD Multipliers
Author :
Sutter, G. ; Todorovich, E. ; Bioul, G. ; Vazquez, M. ; Deschamps, J.-P.
Author_Institution :
Univ. Autonoma de Madrid, Madrid, Spain
Abstract :
This paper presents a number of approaches to implement decimal multiplication algorithms on Xilinx FPGA´s. A variety of algorithms for basic one by one digit multiplication are proposed and FPGA implementations are presented. Later on N by one digit and N by M digit multiplications are studied. Time and area results for sequential and combinational implementations show better figures compared with previous published work. Comparisons against binary fully-optimized multipliers emphasize the interest of the proposed design techniques.
Keywords :
binary codes; combinational circuits; field programmable gate arrays; logic design; optimisation; sequential circuits; BCD multipliers; FPGA implementations; Xilinx FPGA; binary fully-optimized multipliers; binary-coded decimal; combinational implementation; decimal multiplication algorithms; design techniques; one-digit multiplication; sequential implementation; Application software; Combinational circuits; Commercialization; Costs; Digital arithmetic; Encoding; Field programmable gate arrays; Floating-point arithmetic; Hardware; Iterative algorithms; BCD arithmetic; IEEE-745 standard;
Conference_Titel :
Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on
Conference_Location :
Quintana Roo
Print_ISBN :
978-1-4244-5293-4
Electronic_ISBN :
978-0-7695-3917-1
DOI :
10.1109/ReConFig.2009.28
