An optimizing compiler method to avoid partial invalid PLC instructions

Author

Yi, Yan ; Haidan, Chen

Author_Institution

Inst. of Intell. & Software Technol., Hangzhou Dianzi Univ., Hangzhou, China

fYear

2010

fDate

4-7 July 2010

Firstpage

80

Lastpage

83

Abstract

A ladder diagram is read from left to right and top to bottom. The complexity and length of the rungs decide scanning time of a ladder diagram. CPU resources are always seriously occupied by useless instructions when PLC control systems are on the run time, which seriously slow down the system responses. In order to solve this problem, a compilation method is proposed to optimize PLC programme to avoid the execution of partially useless instructions. According to the result of experiments, the performance of PLC system is improved by this method, especially for the ladder diagram containing counter or timer function.

Keywords

instruction sets; optimising compilers; programmable controllers; CPU resource; PLC control system; ladder diagram; optimizing compiler method; partial invalid PLC instruction; rung; scanning time; Biological system modeling; Complexity theory; Field programmable gate arrays; Input variables; Optimization; Radiation detectors; Software;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics (ISIE), 2010 IEEE International Symposium on

Conference_Location

Bari

Print_ISBN

978-1-4244-6390-9

Type

conf

DOI

10.1109/ISIE.2010.5637893

Filename

5637893