A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks

Multivariate polynomial interpolation is a key computation for the reverse engineering of genetic networks modeled by finite fields. Faster implementations of such algorithms are needed to cope with the increasing quantity and complexity of genetic data. Our implementation of an interpolation methodology to FPGA has led us to identify a systolic array-based hardware architecture that is useful for performing at least three interpolation sub-tasks: Boolean cover, uniqueness, and multivariate polynomial addition. We present a generalization of these algorithms that simplifies mapping to the systolic-array structure, as well as control and storage considerations to guarantee correct results when the input sequence is longer than the processing array. The three interpolation sub-tasks were modeled and implemented to FPGA using the proposed structure, obtaining speedups up to 172x when compared to a software implementation, while achieving low resource utilization.