High performance copper and low-k interconnect technology fully compatible to 90nm-node SOC application (CMOS4)

Author

Inohara, M. ; Tamura, L. ; Yamaguchi, T. ; Koike, H. ; Enomoto, Y. ; Arakawa, Shin´ichi ; Watanabe, T. ; Ide, E. ; Kadomura, S. ; Sunouchi, K.

Author_Institution

Syst. LSI Div., Toshiba Corp., Yokohama, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

77

Lastpage

80

Abstract

Dual damascene copper and low-k (k=2.9) interconnect technology for 90nm-node was successfully integrated. Structure and process are optimized to be compatible to transistor, memories, and packaging with consideration of RC delay and crosstalk between lines. Especially, aspect ratio of metal1 was carefully studied with electromigration durability data and DRAM pause time distribution data, because bit lines of embedded DRAM were formed with metal1. In order to demonstrate feasibility for manufacturing, six copper metal layers were fabricated on transistors and memories.

Keywords

CMOS digital integrated circuits; DRAM chips; copper; crosstalk; delays; electromigration; integrated circuit interconnections; integrated circuit manufacture; integrated circuit packaging; integrated circuit reliability; system-on-chip; 90 nm; CMOS4; DRAM pause time distribution data; RC delay; SOC application; aspect ratio; bit lines; crosstalk; dual damascene copper; electromigration durability data; embedded DRAM; low-k interconnect technology; packaging; CMOS technology; Copper; Coupling circuits; Delay; Integrated circuit interconnections; Large scale integration; Leakage current; Manufacturing processes; Packaging; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175783

Filename

1175783