Title :
Low Power RTL Exploration Mechanism Based on the Cache Parameters
Author :
Silva-Filho, A.G. ; Lima, S.M.L. ; Cox, F.C.L.
Author_Institution :
Inf. Center (CIn), Fed. Univ. of Pernambuco (UFPE), Recife, Brazil
Abstract :
Cache memory is a usual architecture component, and has the function of increasing the system´s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases.
Keywords :
cache storage; microprocessor chips; power aware computing; Mibench suite; NIOS II processor; XiRisc suite; automated architecture exploration mechanism; cache memory hierarchy parameter variation; low power RTL exploration mechanism; Analytical models; Cache memory; Circuits; Computational modeling; Computer architecture; Data mining; Energy consumption; Field programmable gate arrays; Space exploration; System performance; Cache Memory; Embedded Systems; Exploration Mechanism; FPGA; Low Power Design; NIOSII; SoC;
Conference_Titel :
Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on
Conference_Location :
Quintana Roo
Print_ISBN :
978-1-4244-5293-4
Electronic_ISBN :
978-0-7695-3917-1
DOI :
10.1109/ReConFig.2009.63
