DPL on Stratix II FPGA: What to Expect?

FPGA design of side channel analysis countermeasure using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing, whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally prove that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, the gain is lower than for ASICs. We expect that an in-depth analysis of routing resources power consumption could help bridge the gap.