Comparison and analysis of combinational circuits using different logic styles

In digital VLSI, power dissipation has become a prime constraint. Many design architecture and techniques have been developed to reduce power dissipation. In this paper implementation of combinational circuits such as logic gates, adders and multipliers in Gate diffusion input (GDI) technique and its comparison with other logic styles is presented. This technique allows reduce power consumption, transistor count and area while maintaining low complexity of logic design. The design is simulated using Mentor Graphics Design Architect.