DocumentCode

3128649

Title

A 200MFLOPS 100MHz 64b BICMOS Vector-pipelined-processor

Author

Okamoto, F. ; Hagihara, Y. ; Ohkubo, C. ; Sekine, Y. ; Nishi, N. ; Yamada, H. ; Enomoto, T.

Author_Institution

NEC Corporation

fYear

1991

fDate

13-15 Feb. 1991

Firstpage

256

Lastpage

257

Keywords

Adders; Arithmetic; BiCMOS integrated circuits; Clocks; Delay effects; Logic circuits; Logic gates; Pipelines; Power dissipation; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-87942-644-6

Type

conf

DOI

10.1109/ISSCC.1991.689150

Filename

689150