Modelling and analysis of power dissipation in single electron logic

A new analytical model for Single Electron Transistors (SETs) that can be used for co-simulation with CMOS is developed and validated with Monte Carlo simulation. The model includes temperature dependence, device asymmetry and background charge effects. A detailed physical parameter extraction procedure for asymmetric SETs is reported. An analytical approach is subsequently developed to investigate and accurately predict the power dissipation of SET inverters. Static power, as the main mechanism of SET logic power dissipation, and contributions of dynamic and temperature-dependent leakage power are derived and critically discussed. It is shown that SET asymmetry can be exploited to significantly reduce SET logic power dissipation with negligible impact on propagation delay.