The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction

Author

Baumann, R.

Author_Institution

Silicon Technol. Dev. Group, Texas Instrum. Inc., Dallas, TX, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

329

Lastpage

332

Abstract

The soft error rate (SER) of advanced CMOS devices is higher than all other reliability mechanisms combined. Memories can be protected with error correction circuitry but SER in logic may limit future product reliability. Memory and logic scaling trends are discussed along with a method for determining logic SER.

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; SRAM chips; alpha-particle effects; error correction; integrated circuit reliability; integrated circuit testing; neutron effects; sequential circuits; space vehicle electronics; DRAM product die; SER performance; SRAM test chips; accelerated neutron experiments; advanced CMOS devices; alpha particle experiments; error correction circuitry; logic scaling trends; memory scaling trends; radiation effects; reliability mechanisms; sequential logic circuits; soft error rate; spacecraft electronics; technology scaling; CMOS logic circuits; CMOS technology; Circuit testing; Error analysis; Error correction; Latches; Logic devices; Logic testing; Random access memory; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175845

Filename

1175845