Implementation aspects of lattice bilinear digital ladder filters

Author

Signell, Svante ; Konradsson, P. ; Harnefors, Lennart

Author_Institution

Ericsson Radio Syst., Stockholm, Sweden

Volume

2

fYear

1997

fDate

2-4 Jul 1997

Firstpage

649

Abstract

Lattice bilinear digital ladder filters (BDLF) were introduced in a previous paper. Here, some results regarding hardware implementation of lattice BDLFs are presented. Both direct implementation of the signal flow graph (SFG) and state-space implementation are considered. At the most, a critical path of two multipliers and four adders is obtained, enabling sampling rates up to 40 and 20 MHz, for the state-space and SFG implementations, respectively. This combined with the low sensitivity inherent with the BDLF structure allowing implementation with short word-length multipliers-clearly indicates that lattice BDLFs are viable contenders to circulator lattice wave digital filters for high-speed applications

Keywords

adders; bilinear systems; digital filters; filtering theory; ladder filters; lattice filters; multiplying circuits; signal flow graphs; signal sampling; state-space methods; 20 MHz; 40 MHz; adders; circulator lattice wave digital filters; critical path; direct implementation; hardware implementation; high-speed applications; lattice bilinear digital ladder filters; low sensitivity; sampling rates; short wordlength multipliers; signal flow graph; state-space implementation; Adders; Delay; Digital filters; Digital signal processing; Flow graphs; Hardware; Inspection; Lattices; Sampling methods; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Digital Signal Processing Proceedings, 1997. DSP 97., 1997 13th International Conference on

Conference_Location

Santorini

Print_ISBN

0-7803-4137-6

Type

conf

DOI

10.1109/ICDSP.1997.628433

Filename

628433