Title :
Research Challenges on 2-D and 3-D Network-on-Chips
Author :
Matsutani, Hiroshi
Author_Institution :
Dept. of ICS, Keio Univ., Yokohama, Japan
Abstract :
The advances in semiconductor technology allow us to integrate a number of processing cores on a single chip or a single package. These many-core processors are expected to boost a wide range of applications from high-performance computing, cyber-physical computing, cloud, and big data processing. This tutorial first introduces recent many-core processors and then focuses on fundamental technologies of 2-D and 3-D Network-on-Chip architectures in terms of network topology, routing algorithm, and router architecture. Recent research challenges on 2-D and 3-D Network-on-Chip architectures, such as 2-D and 3-D wireless technologies, are also surveyed.
Keywords :
network routing; network topology; network-on-chip; 2D network-on-chips; 3D network-on-chips; network topology; network-on-chip architectures; router architecture; routing algorithm; Bandwidth; Computer architecture; Network topology; Program processors; Routing; System-on-chip; Wireless communication; 3-D NoCs; Network-on-Chips (NoCs); interconnection networks;
Conference_Titel :
Computing and Networking (CANDAR), 2013 First International Symposium on
Conference_Location :
Matsuyama
Print_ISBN :
978-1-4799-2795-1
DOI :
10.1109/CANDAR.2013.12