75 nm damascene metal gate and high-k integration for advanced CMOS devices

Author

Guillaumot, B. ; Garros, X. ; Lime, F. ; Oshima, K. ; Tavel, B. ; Chroboczek, J.A. ; Masson, P. ; Truche, R. ; Papon, A.M. ; Martin, F. ; Damlencourt, J.F. ; Maitrejean, S. ; Rivoire, M. ; Leroux, C. ; Cristoloveanu, S. ; Ghibaudo, G. ; Autran, J.L. ; Sko

Author_Institution

STMicroelectronics, Crolles, France

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

355

Lastpage

358

Abstract

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit metallisation; integrated circuit noise; low-power electronics; 1.35 nm; 75 nm; 75 nm damascene metal gate; EOT; LF noise; TEM; advanced CMOS process; charge pumping; high temperature transport; high-k dielectrics; high-k integration; low gate current; low standby power applications; low temperature transport; split C-V characteristics; Breakdown voltage; CMOS process; Capacitance-voltage characteristics; High K dielectric materials; High-K gate dielectrics; Interface states; MOSFET circuits; Microstrip; Stress; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175851

Filename

1175851