DocumentCode
3129181
Title
A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length
Author
Lu, J.P. ; Miles, D. ; Zhao, J. ; Gurba, A. ; Xu, Y. ; Lin, C. ; Hewson, M. ; Ruan, J. ; Tsung, L. ; Kuan, R. ; Grider, T. ; Mercer, D. ; Montgomery, C.
Author_Institution
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
371
Lastpage
374
Abstract
A novel nickel self-aligned silicide (SALICIDE) process technology has been developed for CMOS devices with physical gate length of sub-40 nm. The excess silicidation problem due to edge effect is effectively solved by using a low-temperature, in-situ formed Ni-rich silicide. With this new process, excess poly gate silicidation is prevented. Island diode leakage current and breakdown voltage are also improved.
Keywords
CMOS integrated circuits; MOSFET; integrated circuit metallisation; leakage currents; nickel compounds; semiconductor device breakdown; 30 to 40 nm; CMOS; NiSi; SALICIDE process technology; breakdown voltage; edge effect; excess silicidation problem; island diode leakage current; low-temperature Ni-rich silicide; physical gate length; CMOS process; CMOS technology; Diodes; Instruments; Nickel; Silicidation; Silicides; Silicon; Temperature; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175855
Filename
1175855
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