Title :
Analysis and guidelines for high-speed VLSI system interconnections
Author_Institution :
IBM Gen. Technol. Div., Essex Junction, VT, USA
Abstract :
A description is given of the modeling and analysis procedures used to generate system-level wiring rules and net delay equations for IBM´s 1.0-μn CMOS standard-cell design system VLSI products. Business rationale, circuit and package models, and analysis methods are reviewed, as is a sample of the result in a midrange processor environment. High-performance single and multichip packages are used in the analysis, as are high-reliability under- and over-voltage specifications. These choices target the analysis for high-cost, high-performance applications
Keywords :
CMOS integrated circuits; VLSI; delay lines; logic design; printed circuits; 1 micron; CMOS; analysis; analysis methods; business rationale; circuit models; guidelines; high-speed VLSI system interconnections; midrange processor environment; modeling; multichip packages; net delay equations; overvoltage specifications; package models; standard-cell design system VLSI products; system-level wiring rules; undervoltage specifications; Delay; Equations; Guidelines; Integrated circuit interconnections; Logic testing; Packaging; Product design; Timing; Very large scale integration; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20922
