A Pipelined Program Decompression Engine Generator Based on Partial Field-Partitioned (PFP) Compression Technique for Embedded Systems

For rare instructions, the decompression cost is higher than the saving due to compression. This paper presents a new technique, called partial field partitioned compressing so that some rare instructions are field-partitioned into smaller parts and then, compress these parts in the same field to reduce the cost. A software program has been designed to generate a Verilog (a Hardware Description Language) description of a decompression engine for each compressed ARM program. Then, the description is synthesized using Design Compiler of the Synopsys Co. The synthesized results for several benchmarks show that all cases are better than the results of our previous versions.