A highly manufacturable high density embedded SRAM technology for 90 nm CMOS

Author

Fukaura, Yasuhiro ; Kasai, Kunihiro ; Okayama, Yasunori ; Kawasaki, Hirohisa ; Isobe, Kazuaki ; Kanda, Masahiko ; Ishimaru, Kazunari ; Ishiuchi, Hidemi

Author_Institution

SoC Res. & Dev. Center, Toshiba Corp., Yokohama, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

415

Lastpage

418

Abstract

A highly manufacturable high density embedded SRAM technology with a 0.8 /spl mu/m/sup 2/ cell for the 90 nm technology node has been developed. Based on a cell layout study by lithography simulation, both cell layout and key processes were carefully optimized and scaled down from those of 100 nm technology. The fabricated SRAM using 0.25 /spl mu/m well isolation and 0.1 /spl mu/m contacts showed good functionality down to VDD=0.6 V. An electrical fuse utilizing MOSFETs was also developed for redundancy to avoid Cu/low-k BEOL damage from laser blow.

Keywords

CMOS memory circuits; SRAM chips; circuit optimisation; electric fuses; embedded systems; integrated circuit layout; 0.1 micron; 0.6 V; 90 nm; 90 nm CMOS; MOSFET; cell layout; electrical fuse; functionality; highly manufacturable high density embedded SRAM technology; key process optimization; lithography simulation; redundancy; well isolation; CMOS technology; Costs; Delay lines; Isolation technology; Large scale integration; Lithography; Manufacturing; Random access memory; Research and development; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175867

Filename

1175867